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(R)
VND810MSP
DOUBLE CHANNEL HIGH SIDE DRIVER
TYPE VND810MSP (*) Per each channel
RDS(on) 150 m (*)
IOUT 0.6 A (*)
VCC 36 V
CMOS COMPATIBLE INPUTS OPEN DRAIN STATUS OUTPUTS s ON STATE OPEN LOAD DETECTION s OFF STATE OPEN LOAD DETECTION s SHORTED LOAD PROTECTION s UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN s PROTECTION AGAINST LOSS OF GROUND s VERY LOW STAND-BY CURRENT
s s s
10
1
PowerSO-10TM
ORDER CODES
PACKAGE TUBE T&R PowerSO-10TM VND810MSP VND810MSP13TR
REVERSE BATTERY PROTECTION (**)
DESCRIPTION The VND810MSP is a monolithic device designed in STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation BLOCK DIAGRAM
combined with thermal shutdown and automatic restart protects the device against overload. The current limitation threshold is aimed at detecting the 21W/12V standard bulb as an overload fault. The device detects open load condition both in on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection.
Vcc
Vcc CLAMP
OVERVOLTAGE UNDERVOLTAGE
GND INPUT1 STATUS1
CLAMP 1 OUTPUT1 DRIVER 1 CLAMP 2 CURRENT LIMITER 1 OVERTEMP. 1 LOGIC OPENLOAD ON 1 CURRENT LIMITER 2 DRIVER 2 OUTPUT2
INPUT2 OPENLOAD OFF 1 STATUS2 OPENLOAD OFF 2 OVERTEMP. 2 OPENLOAD ON 2
(**) See application schematic at page 8
Rev. 1
1/19
July 2004
1
VND810MSP
ABSOLUTE MAXIMUM RATING
Symbol VCC - VCC - IGND IOUT - IOUT IIN Istat Parameter DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) - INPUT VESD - STATUS - OUTPUT - VCC Maximum Switching Energy (L=400mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=0.9A) Power Dissipation TC=25C Junction Operating Temperature Case Operating Temperature Storage Temperature Value 41 - 0.3 - 200 Internally Limited -6 +/- 10 +/- 10 4000 4000 5000 5000 225 52 Internally Limited - 40 to 150 - 55 to 150 Unit V V mA A A mA mA V V V V mJ W C C C
EMAX Ptot Tj Tc Tstg
CONFIGURATION DIAGRAM (TOP VIEW) & SUGGESTED CONNECTIONS FOR UNUSED AND N.C. PINS
GROUND INPUT 1 STATUS 1 STATUS 2 INPUT 2
6 7 8 9 10 11 VCC
5 4 3 2 1
OUTPUT 1 OUTPUT 1 N.C. OUTPUT 2 OUTPUT 2
Connection / Pin Status Floating X To Ground
N.C. X X
Output X
Input X Through 10K resistor
CURRENT AND VOLTAGE CONVENTIONS
IS IIN1 INPUT 1 VIN1 VSTAT1 ISTAT1 STATUS 1 IIN2 INPUT 2 VIN2 ISTAT2 STATUS 2 VSTAT2 GND OUTPUT 2 VOUT2 IGND OUTPUT 1 IOUT2 VOUT1 IOUT1
VF1 (*)
VCC
VCC
(*) VFn = VCCn - VOUTn during reverse battery condition
2/19
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VND810MSP
THERMAL DATA
Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Value 2.4 52.4 (1) 37 (2) Unit C/W C/W
(1) When mounted on a standard single-sided FR-4 board with 0.5 cm 2 of Cu (at least 35m thick). Horizontal mounting and no artificial air flow. (2) When mounted on a standard single-sided FR-4 board with 6 cm 2 of Cu (at least 35m thick). Horizontal mounting and no artificial air flow.
ELECTRICAL CHARACTERISTICS (8VSymbol VCC (**) VUSD (**) VOV (**) RON Parameter Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down On State Resistance Test Conditions Min 5.5 3 36 Typ 13 4 Max 36 5.5 150 12 12 5 0 -75 320 40 25 7 50 0 5 3 Unit V V V m m A A mA A A A A
IOUT =0.5A; Tj=25C IOUT =0.5A; VCC>8V Off State; VCC=13V; VIN=VOUT=0V Off State; VCC=13V; VIN=VOUT=0V;
IS (**)
Supply Current
Tj=25C
On State; VCC=13V; VIN=5V; IOUT =0A IL(off1) IL(off2) IL(off3) IL(off4)
(**) Per device
Off Off Off Off
State State State State
Output Current Output Current Output Current Output Current
VIN=VOUT =0V VIN=0V; VOUT=3.5V VIN=VOUT =0V; VCC=13V; Tj =125C VIN=VOUT =0V; VCC=13V; Tj =25C
SWITCHING (V CC=13V)
Symbol td(on) td(off) dVOUT/ dt(on) dVOUT/ dt(off) Parameter Turn-on Delay Time Turn-off Delay Time Turn-on Voltage Slope Test Conditions RL=13 from VIN rising edge to VOUT =1.3V RL=13 from VIN falling edge to VOUT =11.7V RL=13 from VOUT=1.3V to VOUT =10.4V RL=13 from VOUT=11.7V to VOUT =1.3V Min Typ 30 30 See relative diagram See relative diagram Max Unit s s V/s
Turn-off Voltage Slope
V/s
LOGIC INPUT
Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage Test Conditions VIN = 1.25V VIN = 3.25V IIN = 1mA IIN = -1mA 0.5 6 6.8 -0.7 Min 1 3.25 10 8 Typ Max 1.25 Unit V A V A V V V
3/19
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VND810MSP
ELECTRICAL CHARACTERISTICS (continued) VCC - OUTPUT DIODE
Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=0.5A; Tj=150C Min Typ Max 0.6 Unit V
STATUS PIN
Symbol VSTAT ILSTAT CSTAT VSCL Parameter Status Low Output Voltage Status Leakage Current Status Pin Input Capacitance Status Clamp Voltage Test Conditions ISTAT = 1.6 mA Normal Operation; VSTAT= 5V Normal Operation; VSTAT= 5V ISTAT = 1mA ISTAT = - 1mA 6 6.8 -0.7 Min Typ Max 0.5 10 100 8 Unit V A pF V V
PROTECTIONS (see note 1)
Symbol TTSD TR Thyst tSDL Ilim Vdemag Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status Delay in Overload Conditions Current limitation Turn-off Output Clamp Voltage Test Conditions Min 150 135 7 Typ 175 15 20 0.6 5.5VTj>TTSD
Note 1: To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles
OPENLOAD DETECTION
Symbol IOL tDOL(on) VOL tDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V IOUT=0A VIN=0V 1.5 2.5 Min 20 Typ 40 Max 80 200 Unit mA s V s
3.5 1000
OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT> VOL VINn VINn
OVER TEMP STATUS TIMING Tj > TTSD
VSTAT n
VSTAT n tSDL tDOL(off) tDOL(on) tSDL
4/19
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1
VND810MSP
Switching time Waveforms
VOUTn 90% 80%
dVOUT/dt(on)
dVOUT/dt(off)
10% t VINn
td(on)
td(off)
t
TRUTH TABLE
CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H STATUS H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L
5/19
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VND810MSP
ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2
I C C C C C C
IV C C C C C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
6/19
1
1
VND810MSP
Figure1: Waveforms
NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VCC INPUTn OUTPUT VOLTAGEn STATUSn undefined
VUSD VUSDhyst
OVERVOLTAGE
VCCVOV
VCC INPUTn OUTPUT VOLTAGEn STATUSn OPEN LOAD with external pull-up INPUTn OUTPUT VOLTAGEn STATUSn
VOUT>VOL
VOL
OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj INPUTn OUTPUT CURRENTn STATUSn
TTSD TR
7/19
1
VND810MSP
APPLICATION SCHEMATIC
+5V +5V +5V VCC Rprot STATUS1 Dld C Rprot INPUT1 OUTPUT1 Rprot STATUS2
Rprot
INPUT2
GND
OUTPUT2
RGND VGND
DGND
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / IS(on)max. 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary
depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggest to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.
8/19
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1
VND810MSP
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT =(VPU/(RL+RPU))RLC I/Os PROTECTION:
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k.
Open Load detection in off state
V batt.
VPU
VCC RPU INPUT DRIVER + LOGIC OUT + R STATUS VOL RL IL(off2)
GROUND
9/19
1
VND810MSP
Off State Output Current
IL(off1) (uA)
1.6 1.44 1.28 1.12 0.96 0.8 0.64 0.48 0.32 0.16 0 -50 -25 0 25 50 75 100 125 150 175
High Level Input Current
Iih (uA)
5
Off state Vcc=36V Vin=Vout=0V
4.5
Vin=3.25V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Input Clamp Voltage
Vicl (V)
8 7.8
Status Leakage Current
Ilstat (uA)
0.05
Iin=1mA
7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175 0 -50 -25 0 25 50 75 100 125 150 175 0.01 0.02 0.03 0.04
Vstat=5V
Tc (C)
Tc (C)
Status Low Output Voltage
Vstat (V)
0.8 0.7
Status Clamp Voltage
Vscl (V)
8 7.8
Istat=1.6mA
0.6
Istat=1mA
7.6 7.4
0.5 0.4 0.3 0.2
7.2 7 6.8 6.6 6.4
0.1 0 -50 -25 0 25 50 75 100 125 150 175
6.2 6 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
10/19
1
VND810MSP
On State Resistance Vs Tcase
Ron (mOhm)
400 350 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 125 150 175
On State Resistance Vs VCC
Ron (mOhm)
400 350
Iout=1A Vcc=8V; 13V & 36V
Iout=1A
300 250 200 150 100
Tc= 125C
Tc= 25C
Tc= - 40C
50 0 5 10 15 20 25 30 35 40
Tc (C)
Vcc (V)
Openload On State Detection Threshold
Iol (mA)
60 55 50 45 40 35 30 25
Input High Level
Vih (V)
3.6 3.4
Vcc=13V Vin=5V
3.2 3 2.8 2.6 2.4
20 15 10 -50 -25 0 25 50 75 100 125 150 175 2.2 2 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Input Low Level
Vil (V)
2.6 2.4 2.2
Input Hysteresis Voltage
Vhyst (V)
1.5 1.4 1.3 1.2
2 1.8 1.6 1.4
1.1 1 0.9 0.8 0.7
1.2 1 -50 -25 0 25 50 75 100 125 150 175
0.6 0.5 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
11/19
1
VND810MSP
Overvoltage Shutdown
Vov (V)
50 48 46 44 42 40 38 36 34 32 30 -50 -25 0 25 50 75 100 125 150 175
Openload Off State Voltage Detection Threshold
Vol (V)
5 4.5
Vin=0V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Turn-on Voltage Slope
dVout/dt(on) (V/ms)
1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Turn-off Voltage Slope
dVout/dt(off) (V/ms)
500 450
Vcc=13V Rl=13Ohm
400 350 300 250 200 150 100 50 0 -50
Vcc=13V Rl=13Ohm
-25
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
ILIM Vs Tcase
Ilim (A)
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175
Vcc=13V
Tc (C)
12/19
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VND810MSP
Maximum turn off current versus load inductance
ILMAX (A) 10
A
1
B C
0.1 1 10 100 L(mH) 1000 10000
A = Single Pulse at TJstart=150C B= Repetitive pulse at T Jstart=100C C= Repetitive Pulse at T Jstart=125C Conditions: VCC=13.5V Values are generated with R L=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization
t
13/19
VND810MSP
PowerSO-10TM THERMAL DATA
PowerSO-10TM PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: from minimum pad lay-out to 8cm2).
Rthj-amb Vs PCB copper area in open box free air condition
RTHj_amb (C/W)
55
Tj-Tamb=50C
50 45 40 35 30
0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
14/19
VND810MSP
PowerSO-10 Thermal Impedance Junction Ambient Single Pulse
ZTH (C/W) 1000
100
0.5 cm 2 6 cm2
10
1
0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000
Thermal fitting model of a double channel HSD in PowerSO-10
Pulse calculation formula
Z TH = R TH + Z THtp ( 1 - )
where
= tp T
0.5 0.35 1.8 1.1 0.8 12 37 0.0001 7.00E-04 0.008 0.3 0.75 3 6
Thermal Parameter
Tj_1
Pd1 C1 C2 C1 C2 C3 C4 C5 C6
R1
R2
R3
R4
R5
R6
Tj_2
R1 Pd2
R2
T_amb
Area/island (cm2) R1 (C/W) R2 (C/W) R3( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
22
5
15/19
VND810MSP
PowerSO-10TM MECHANICAL DATA
DIM. A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) (*)
(*) Muar only POA P013P
mm. MIN. 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 1.27 1.25 1.20 13.80 13.85 0.50 1.20 0.80 0 2 1.80 1.10 8 8 0.047 0.031 0 2 1.35 1.40 14.40 14.35 0.049 0.047 0.543 0.545 TYP MAX. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 MIN. 0.132 0.134 0.000 0.016 0.014 0.013 0.009 0.370 0.291 0.366 0.283 0.287 0.232 0.232
inch TYP. MAX. 0.144 0.142 0.004 0.024 0.021 0.022 0.0126 0.378 0.300 0.374 300 0.295 0.240 0.248 0.050 0.053 0.055 0.567 0.565 0.002 0.070 0.043 8 8
B
0.10 A B
10
H
E
E2
E
E4
1
SEATING PLANE e
0.25
B
DETAIL "A"
A
C D = D1 = = = SEATING PLANE
h
A F A1
A1
L DETAIL "A"
P095A
16/19
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VND810MSP
PowerSO-10TM SUGGESTED PAD LAYOUT
14.6 - 14.9
B
TUBE SHIPMENT (no suffix)
CASABLANCA MUAR
C
10.8 - 11 6.30
A A
C
0.67 - 0.73 1 2 3 4 5 10 9 8 7 6 0.54 - 0.6
B
9.5
All dimensions are in mm.
1.27
Base Q.ty Bulk Q.ty Tube length ( 0.5) Casablanca Muar 50 50 1000 1000 532 532
A
B
C ( 0.1) 0.8 0.8
10.4 16.4 4.9 17.2
TAPE AND REEL SHIPMENT (suffix "13TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 24 4 24 1.5 1.5 11.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
17/19
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VND810MSP
REVISION HISTORY
Date Revision - Minor changes - Current and voltage convention update (page 2). - "Configuration diagram (top view) & suggested connections for unused and n.c. pins" insertion (page 2). Jul 2004 1 - 6 cm2 Cu condition insertion in Thermal Data table (page 3). - VCC - OUTPUT DIODE section update (page 4). - PROTECTIONS note insertion (page 4) - Revision History table insertion (page 18). - Disclaimers update (page 19). Description of Changes
18/19
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VND810MSP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http://www.st.com
19/19
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